Verilog Simulator in Swift

Simulating Verilog means implementing a language and a scheduler at once: four-state logic on arbitrary bit widths, the standard's intricate self-determination rules for expression width and signedness, blocking versus non-blocking assignment semantics, event-driven scheduling with delays, and the system tasks ($display and friends) through which a design reports its own behavior. Corner cases in width, sign extension, and part-selects are exactly where independent simulators disagree, and where a correct one must not.

The task is cross-domain by design: hardware-description-language semantics, implemented in Swift, judged against Icarus Verilog (an established open-source simulator) running live on the same designs.

Implement a Verilog simulator in the Swift package at /app, writing sources only as .swift files under Sources/vsim/ (standard library plus Foundation only, with Package.swift left as provided), and building offline with swift build -c release into /app/.build/release/vsim.

• Invoked as vsim <design.v>, it reads a self-contained, self-driving Verilog-2005 design, runs it to completion, prints its output to stdout and diagnostics to stderr, and exits 0.
• Output is compared ignoring trailing whitespace and tool-diagnostic lines: what matters is what the design itself prints.
• The example designs in ivtest/ (listed in ivtest/manifest.tsv) define the scope, from full behavioral regression tests to generated operator/width/sign-corner expression testbenches.

A ready-to-build Swift package at /app and the ivtest/ corpus: 1,528 designs listed in manifest.tsv, drawn from the Icarus Verilog regression suite (ivltests/) and from VlogHammer expression modules wrapped as self-driving testbenches (vlh/), each paired with its expected output under ivtest/goldens/. build_and_test.sh builds the simulator and checks it against the corpus. The Swift toolchain is preinstalled and the machine is offline; Icarus Verilog itself is locked root-only, unreachable by the agent.

A clean-room verifier, separate from the agent's environment, reconstructs the project from a pristine scaffold plus only the agent's .swift sources, rebuilds it offline as a non-root user (600-second cap), and grades it differentially against live Icarus Verilog: for every graded design, the root-only iverilog/vvptoolchain computes the expected output at verify time, so there are no stored answers to replay, and the candidate's output must match it under the whitespace/diagnostic-insensitive comparator.

• Reward is the fraction of graded designs passed. Designs Icarus Verilog itself cannot run are skipped, as are non-differential goldens (bare pass/fail verdicts reconstructible from the source); those cannot earn credit without real simulation.
• An unmodified starting scaffold, a project that does not build offline, a missing binary, or zero passed designs all score 0.
• Per-design caps of 10 seconds for each side inside a 3300-second suite budget.